Physical Design Engineer
- Employment Type: Full-Time
- Work Location: Onsite / Hybrid
- Experience 2- 5 Years
We are seeking a skilled Physical Design Engineer to join our VLSI/ASIC design team. The ideal candidate will be responsible for the complete physical implementation flow, from netlist to GDSII, ensuring timing, power, area, and signal integrity requirements are achieved. The candidate should have hands-on experience with industry-standard EDA tools and semiconductor design methodologies.
Key Responsibilities
- Perform complete ASIC physical design implementation, including floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and physical verification.
- Optimize designs for timing, power, congestion, and area.
- Execute static timing analysis (STA) and timing closure.
- Perform IR drop, electromigration (EM), and signal integrity analysis.
- Resolve Design Rule Check (DRC), Layout Versus Schematic (LVS), and Electrical Rule Check (ERC) violations.
- Collaborate with RTL, Design Verification, DFT, and Packaging teams throughout the design cycle.
- Develop and maintain physical design automation scripts using Tcl, Perl, Python, or Shell.
- Support tape-out activities and ensure high-quality design delivery.
- Analyze and resolve physical implementation issues to meet project schedules.
Required Qualifications
- Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.
- 3+ years of experience in ASIC Physical Design.
- Strong understanding of CMOS technology and semiconductor fundamentals.
- Experience with complete physical implementation flow from synthesis to GDSII.
- Knowledge of advanced technology nodes (28nm, 16nm, 7nm, 5nm, or below).
- Experience with low-power design techniques and UPF/CPF is a plus.
Education
- Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related discipline.